Ahh, this all makes sense. This is exactly what I am seeing then. Thanks for all the screenies and the PCMark runs. A couple things that are still puzzling. Take a look at chipset 3.
Logical/Chipset 3 Memory Banks
Bank 0 : 512MB DDR-SDRAM 2.5-3-3-8 (tCL-tRCD-tRP-tRAS) CR2
Bank 1 : 512MB DDR-SDRAM 2.5-3-3-8 (tCL-tRCD-tRP-tRAS) CR2
Bank 2 : 512MB DDR-SDRAM 2.5-3-3-8 (tCL-tRCD-tRP-tRAS) CR2
Channels : 1
Speed : 2x 200MHz (400MHz data rate)
Width : 128-bit
Memory Controller in Processor : Yes
Cores per Memory Controller : 2 Unit(s)
Maximum Memory Bus Bandwidth : 6400MB/s (estimated)
Says Channels 1 ?? Could this be a sandra bug?
Also from PCWizzard look at this..
Memory Controller Information :
Memory Controller : SIMM, DIMM, SDRAM
Number of connectors : 4
Max. Module Size : 1024 MB
Max. Memory Size : 4096 MB
Supported Speed : 70ns, 60ns
Supported Voltages : 3.3v
Error Detection Method : 64-bit ECC
Error Correction Capability : Unspecified
Current/Supported Interleave : 1-way/1-way
Current supported Interleave = 1 way
?
This should be dual bank interleave I would think. That is why I thougt the chipset is not initializing properly with both banks populated. The bus effieciency is less than 70 percent as well. Maybe the boys over at HCP could shed some light on what the supported interleave is on the ULI chipset and why the 1 channel thing comes up in sandra.